The Dynamic operative memory (Dynamic RAM DRAM) is used in majority of the systems to operative memory personal computer. The Main advantage of this type to memories consists in that that her(its) cells are packed much tightly i.e. in small microcircuit possible to pack much bits, but signifies, on their base possible to build the memory to greater capacity.

The Cells to memories in microcircuit DRAM this tiny capacitors, which hold the charges. The Problems connected with memory of this type, is caused that that she dynamic i.e. must be constantly regenerated, since otherwise electric charges in capacitor of the memories will flow down , and data will be lost. The Regeneration occurs, when controller to memories of the system takes the tiny break and addresses to all lines given in microcircuit of the memories. The Majority of the systems has a controller to memories (usually built in in set of the microcircuits of the system charge), which is adjusted on corresponding to industry-standards refresh rate, equal 15 мкс.
The Regeneration to memories, regrettably, deprives time beside processor: each cycle to regenerations on duration occupies several cycles of the central processor. In old computer cycles to regenerations could take up to 10% processor time, but in modern system, costs on regeneration form 1% (or less) of processor time. Some systems allow to change the parameters to regenerations by means of program of the installation parameter CMOS, but increase of time between cycles of the regenerations can bring about that that in some cell of the memories charge стечет , but this will cause the malfunction to memories. In most cases надежнее to keep recommended or given by default refresh rate.

In device DRAM for keeping of one bit is used only one transistor and pair capacitor so they more spacious, than microcircuits of the other types to memories. The Transistor for each однозарядного of the register DRAM uses the condition of the adjacent capacitor for reading. If capacitor is charged, in cell recorded 1; if charge no recorded 0. The Charges in tiny capacitor all time flow down, that is why memory must be constantly regenerated. Even instant interruption of the presenting the power supply or some malfunction in cycles of the regenerations will bring about loss of the charge in cell DRAM, but, consequently, to loss data.

Presently already not currently use 66-MHZ buses to memories. The Developers DRAM have found the possibility преодолеть this border and extracted some additional advantage by by realization of the synchronous interface. With anisochronous interface processor must expect while DRAM will finish execution their own internal operation, which usually occupy beside 60 ns. With synchronous control DRAM occurs the latchup to information from processor under control system hours. The Triggers remember the address, signals of control and data that allows the processor to execute other tasks. After determined amount of the cycles given become available, and processor can read them with output line.

The Other advantage of the synchronous interface is concluded in that that system watch will assign only temporary borders, necessary DRAM. This excludes need of presence ensemble strobe pulse. Is it As a result simplified entering, t. k. monitor signals of the address data can be saved without participation of the processor and temporary delay. Such a advantage also marketed and in operation of the output.

The Synchronous operative memory, which, being as a whole look like memory of the previous generation (anisochronous DRAM), has one important advantage - a built-in timer of the entering data allows clearly to synchronize presenting to information with tact of the processor, time decreases due to that. Unproductive spent by processor on hold data, which it is necessary to process. There is and other architectral particularities, due to which became possible functioning of this type to memories on frequency 100 MHZ and even above. However, limit is already seen - a modern processors move to more quick buses, and for optimum work with them to come to use other types to memories. But before that moment, when this type to memories will definitively grow old morally, will is sold else millions chip, retail prices on SDRАМ are today found on mark a little above $0,4 for megabyte.

Today most are actively sold modules to memories by volume 32,64 and 128 Mb. Even on the most compact maternal board there is as minimum 2 slots for her(its) accomodations so beside you can be installed from 32 before 256 Mb memories. The Question in that, what her(its) amount real it is necessary. 32 Mb - today this

SIM

Depending on volume, SIMM without checking of parity contains eight microcircuits DRAM, set up with one or with both sides of the card:

• In 4-MB SIMM is installed 8 microcircuits DRAM on the one hand cards
• In 8-MB SIMM is installed 16 microcircuits DRAM - on 8 DRAM with each sides
• In 16-MB SIMM is installed 8 microcircuits DRAM on the one hand cards
• In 32-MB SIMM is installed 16 microcircuits DRAM - on 8 DRAM with each sides

In SIMM with checking of parity one additional bit happens to on each byte to parity. It Is Got that in them each byte corresponds to 9 bits. Earlier met also SIMM with ECC, in which on one byte happened to 10 bits, however in new series of the microcircuits for RS, such, as Triton-II (430HX) and Natoma (440FX), ECC is generated on base usual 9-битных SIMM with checking of parity so user not it is necessary more to try to find the memory with ESS. In 9-m бите SIMM with checking of parity is kept result of the execution to operations XOR on all rest bit. This means that if result of the adding all eight bits presents itself even number, that bit to parity will is a zero. If result of the adding eight bits is an uneven number, that bit to parity will is edinice. Such operation is executed for each eight bits each of byte of the memories. We shall Expect that in memories is kept 8-битное number 01010101. The Amount will is четырем (0+1+0+1+0+1+0+1) i.e. even count;calculate;list so value XOR will is a zero, and in bit of parity will be a recorded zero. If now, for instance, has occurred the malfunction in бите number four, is got 0+1+0+1+?+1+0+1, but keeping in memories XOR-bit will is a zero. If now pack remained seven bits and shall get as a result of operations XOR unit, that, comparable her(it) with recorded in бите of the checking to parity by result to operations XOR, equal zero, is got that lacking numeral must be an unit. Here is so possible restore damaged by informaciyu. ESS presents itself additional bit of protection. He provides the possibility of the correction one bit error and finding error two bits. Insofar this can come in handy? The Casual loss to information, caused gamma ray or the other radiation, meets approximately at 100 years once. Consequently, correction such sort error can be needed the average user approximately at one hundred years once; so indeed this makes sense only for specifically important server. The Programs generate much more error, than equipment, but there is special traps in good program, отлавливающие programme errors.

Each byte in SIMM with checking of parity has one spare bit. This signifies that in SIMM with checking of parity on each eight microcircuits DRAM 1Mx4 (512KB) is required one additional microcircuit DRAM 1Mx4. Exactly in the same way to each microcircuit DRAM 4Mx4 (2MB) needs one additional microcircuit DRAM 4Mx4 or four additional microcircuits DRAM 1Mx4. Thereby, on SIMM with checking of parity possible to see or nine microcircuits DRAM with each sides (all 1Mx4 or all 4Mx4), or eight 4Mx4 on the one hand and four 1Mx4 - with another. So are built SIMM with checking of parity. This - true parity . Logical parity was invented MA Labs and presents itself logic, which defrauds the computer, forcing his(its) consider that in him are set SIMM up with checking of parity then indeed check to parity is not done completely. This, however, allows fraudulently to start the computer, requiring checking to parity, with cheap SIMM, not having checking to parity.

TSOP и SOJ

Exist two different formats of the microcircuits DRAM, which are identified SOJ (Small Outline J-Lead) and TSOP (Thin Small Outline Package). Different sizes and forms of the microcircuits DRAM are understood Under format. As SOJ, so and TSOP are assembled on surfaces of the printed charge with one or with both sides. The Body TSOP more fine, but then SOJ occupies place less.

For practical integer of the final user does not matter, pertains the microcircuit to type SOJ or TSOP. However for production process SOJ удобнее since they in three times fine, than TSOP (3.0mm in contrast with 1.0mm).
Exists two types TSOP. TSOP type I - низкопрофильный body (the height 1.0mm) with contact with small at a walk (0.5mm), emerging on narrow sides on 0.5mm. TSOP type II - низкопрофильный body (the height 1.0mm) with contact with small at a walk (0.5mm), emerging on narrow sides on 1.27mm. The Main advantage TSOP in contrast with SOJ is that TSOP fine and can be used in низкопрофильных product, for instance, as memories in magstripe cards.

Were they Earlier released else two types body - ZIP and DIP. Now they already are not used. For their fabrications was used technology end-to-end hole, and assemble their possible was on one side of the printed board only. DIP look like TSOP that that have a low profile, but occupy the greater area, than ZIP.

Component and not component (true schemes)

Many greater DIMM and SIMM capacity 64MB and 128MB DIMM are released in component (With) and несоставной (T - true ) deskside. Nesostavnye SIMM can work in all system, supporting 64-MB and 128-MB SIMM or DIMM. Usually they consist of 8 or 16 microcircuits by capacity 8MB. Component SIMM and DIMM consist of 32 or more cheap SOJ or TSOP 4x4. Component SIMM, inherently, present itself assembly designs, consisting of SIMM. Sometimes on the market second-hand goods possible to find even component SIMM capacity 16MB and 32MB, in which are used SOJ or TSOP 1x4. Basically, except specifically stipulated events, SIMM and DIMM are an несоставными.

The Main problem component block is that they have more join, than normal несоставные SIMM and DIMM. This enlarges the capacitive resistance and can reduce the velocity of the signal (refer to section Buffered RAM and voltage Many systems, for instance, Macintosh, do not support component SIMM since have not it is enough powerful carrier of the load. Some are a maternal charge Intel and AIR, using AMI BIOS, support component SIMM and DIMM. Component SIMM and DIMM can become the cheap alternative in that event if your budget is limited and if your maternal charge their supports. However do not rage aquisition component SIMM until make sure that they are supported by your maternal charge.

Importance of the type of the block - SIMM and DIMM - and numbers contact

The Processor communicates with memory and card of the expansion through parallel channels of the bus. Herewith he uses the amount a category, equal count;calculate;list available kanalov. For instance, maternal charge on the base Triton-II (430HX) and Natoma (440FX) have 64-class bus to memories (connecting processor with cache-memory, but cache-memory - with the main memory) and 32-class bus PCI (for relationship with card of the expansion). Than broader bus (i.e. than more category), that more information can be sent for one cycle and, became to be, that quicker occurs the issue dannyh. Send rate given - a width of the bus in bit, multiplied by amount operation data communication at second in megahertz and multiplied by volume data. However if size of the bus is 64 categories, that operation of the access to memories is executed with 64 bits to information. The Width of each block SIMM - only 32 bits, consequently, for reception full 64 bits blocks follows to install the vapour(pair). The Access to such two SIMM is realized as to united logical bank RAM. The more early charge, which allow installation of one block SIMM, have a size of the bus, equal whole 32 bits that double reduces the send rate to information. Besides, use four separate SIMM does not give no advantage in contrast with two banks of the same size.

SIMM are connected to bus of the maternal charge by means of 72 gold(en) or tinny (the palladium-nickel) contact. Understandable that SIMM carries the name Single In-line Memory Module since all 72 contacts are located on him in one line. The Early models SIMM had 30 contacts. The Other blocks to memories, for instance, DIMM (Dual In-line Memory Modules), have a size 64 bits (on 128 conclusions) so for bank needs only one module DIMM.

Nearly in 99% maternal charges is used tin (the palladium-nickel), which is inflicted on gold(en) contacts SIMM by means of cathode-anode reaction. The Specialists on semiconductor corrosion confirm that possible when use such contact degree to corrosions does not disturb correct work SIMM since area of the contact small. If this was a truth, the most largest producers SIMM, for instance, NEC, immediately have stopped production SIMM with gold(en) contact. Certainly, work with tin several сложнее since it quicker is covered оксидной by film. The Majority engineer, developping SIMM, according to with that that gold better. Only Intel confirms inverse. However, events to corrosions unknown.

Memory with interleaving

Need for new speediest processor and parallel performing the processes do capacity to memories (reception capacity) narrow revenge modern computer systems. The Interleaving to memories - a method, used for increase of maximum reception capacity, which can provide the computer system in unit of time. However interleaving to memories does not influence upon time of запаздывания memories, which is discussed in section, касающемся cache-memories.

The Interleaving to memories is realized by means of division of the memories on several separate banks, which can process the inquiry for reading or record independently friend from friend, parallel. For instance, in serieses of the microcircuits Intel Orion 450GX (skim with production) for processor Intel Pentium Pro was used four main memories with interleaving, which was organized by means of fission of the memories on four banks. The Limiting case of the interleaving to memories marketed in modern vector суперкомпьютерах SMP (Cray), in which can be before 256 pathways чередующихся banks to memories!

In usual four main systems to memories with interleaving SIMM are logically divided on four banks. When writing given in memory simultaneously can be recorded four lines since each line is written in separate bank regardless of other - parallel. Unlike this, in system without interleaving for ditto time in memory is written only one line. So four main interleaving memory writes and reads given in four times quicker, than memory without interleaving, working with maximum velocity. Voobrazite that can do суперкомпьютер with 256-main interleaving memory! You, probably, heard of similar way of the interleaving given on disk, used in system RAID (refer to section to technical information on hard disk), under which increase to reception capacity of the disk is reached by similar image.

Exists the type to memories, absolutely different from others, - a steady-state operative memory (Static RAM SRAM). She is named so therefore that, in change from dynamic operative memory , for conservation of her(its) contents is not required переодической to regenerations. But this not single her(its) advantage. SRAM has a more high speed, than dynamic operative memory, and can work at the same frequency, as modern processors.

Time of the access SRAM not more than 2 ns, this means that such memory can work synchronous with processor on frequency 500 MHZ or above. However for keeping of each bit in designs SRAM is used кластер from 6 transistors. Use transistor without what or capacitor means that there is no need to in regenerations. While it is given feeding, SRAM will remember that is preserved.
The Microcircuits SRAM are not used for the whole system memory therefore that in contrast with dynamic operative memory speed SRAM much above, but density her(its) much below, but the price rather high. More Low density means that microcircuits SRAM have a greater size though their information capacity much less. The Large number transistor and кластиризованное their accomodation not only enlarges the size SRAM, but also vastly raises the cost of the technological process in contrast with similar parameter for microcircuits DRAM.

In spite of this, developers even so use the memory of the type SRAM for increasing of efficiency RS. But in order to avoid significant increase the cost is fixed only small volume to speediest memory SRAM, which is used as cache-memories. The Cache-memory works at clockrates, close or even equal clockrates of the processor moreover usually exactly this memory is used by processor when reading and record. During operation of the reading, given in speediest cache-memory are beforehand written from operative memory with low speed that is to say from DRAM. So exactly cache-memory allows to shorten the amount simple and enlarge the computer speed as a whole.

Efficiency cache-memories is expressed hit rate, or factor of the success. The Hit rate is an attitude amount ingenious address in cache to the gross amount of the address. The Hit this event, consisting in that that necessary processor given are beforehand read in cache from operative memory; in other words, in the event of hit processor can read given from cache-memories. Unchancy address in cache is considered such, under which controller KESHA has not provided the need for data, residing on specified absolute address. In such event necessary given were not is beforehand scanned in cache-memory so processor must find them in more slow operative memory, rather then in high-speed KESHE.

To minimize rotational latency when sensing by processor given from slow operative memory, in modern personal computer are usually provided two types cache

CACHE - a memory

In velocity, the modern memory of the processor DRAM has very big rotational latency. Rotational latency - time, during which is blocked in memory executes the request of the processor on reading or record. For instance, processor Pentium About, laying on frequency 200MHz, can give the request each 5ns (1/200000000). For comparison - a memory DRAM can answer these requests in 60ns only as soon as. So between processor and PARADISE are installed SRAM (the Steady-state Memory of the RANDOM ACCESS - a steady-state memory with free accesses), velocity what usually lie in interval with 7 before 15ns; she executes the functions of the buffer and is identified the cache-memory.

SRAM, EITHER AS DRAM, - энергозависимой by memory, which saves recorded in her(its) information only before on her(its) there is napryazhenie. Usually she lays vastly quicker, than DRAM, and does not require the wait states. DRAM COST(stand)s more cheaply with is used only two transistors on бите then for SRAM was needed with 6 before 8 transistors on bit.

Koeffmcment CACHE - a hits

The Cache-memory SRAM is used for keeping data, which are directly required processor. The Statistical analysis of the work modern computer shows that beside 90% all data, which requires the processor, is usually found in cache-memories; this value is identified the factor a cache-hits. If processor finds necessary him information in cache-memories, this is identified the cache-hit, otherwise he happens to to search for necessary information in DRAM; such situation is identified the cache-miss.

Since cache-memory SRAM works quicker, than memory DRAM, factor cache-hits of proportional efficient rotational latency of the whole system to memories. If mark factor a cache-hits through H, but rotational latency cache-memories and DRAM - through Tc and Tm accordingly, that efficient (average) rotational latency systems to memories, comprising of itself cache-memory, is defined as Teff= H * Tc + (1-H)*Tm Increase to velocities, connected with presence cache-memories, is defined as attitude Tm to Teff and exponential increases with growth H: S=Tm/Teff = 1/(1-H(1-Tc/Tm))

Cache-memory with direct image

To obtain such high efficiency (and corresponding to values of the factor of the hit), in cache-memory from the main memory must get only the most necessary data. For this exist the different methods of the image kesh-pamyati. the most ingenious is a method of the image cache-memories with associativity on ensemble. However he very built, and to understand, as he works, it is necessary in the beginning to study the methods of the direct image and completely assotiative image.

The most Simplest type of the image is a direct image. The Whole information in memories and in cache-memories is organized in the manner of logical block, which are identified the cache-lines. Given are sent from the main memory in cache-memory in the manner of cache-lines. The Cache-line usually consists of four words. The Word consists of 32 or 64 bits to information. However in cache-memories can be only part cache-lines, prestored in the main memory.

Feature of the module DDR

The Module to memories DDR very looks like module DIMM memories SDRAM. But they have a different connectors. If SDRAM DIMM has 168- contact connector, that DDR DIMM are released with 184 and 200 (SO-DIMM for mobile computer) contact. Consequently, for memory DDR necessary to use the excellent jack. About this does not follow to forget, buying maternal charge. Since sets of the microcircuits, except memories DDR, support and SDRAM, fabrication of the charge, on which will be both types jack, does not present no technical problem. For instance, company Micro-Star International (MSI) has adjusted the production of such charge Pro266 Master (MS-6366). On given moment exists two specifications DDR SDRAM PC1600 works at frequency 200 MHZ and has peak reception capacity 1,6 Gbayt/with, but PC2100 on frequency 266 MHZ and has peak reception capacity 2,1 Gbayt/with.

Using to memories DDR SDRAM possible to divide into three areas servers, workstation, ноутбуки. For Unix and NT-server is used регистровая memory she more reliable in work, but cost(stand)s cherish, than unbuffered, which is used in home PC and workstation. At desire you may in its home computer to use and регистровую memory, but expenseses will not justified. Also to account of the absence of the extended logic and as can be seen from name, what that nor was a buffer data, unbuffered memory more high-speed, than регистровая. Aloof cost(stand)s DDR Small Outline DIMM, applicable in mobile computer. She has a smaller size (2,7 inches unlike modules 184-pin size 5,25 inches) and is calculated on horizontal accomodation in maternal charge.
In contrast with SDRAM, the memory DDR SDRAM has low энергопотребление and eats from voltage 2,5 volts. At present unbuffered memory is released in module by volume from 64 before 512 Mbytes (soon must appear 1 Gbayt modules), but регистровая from 128 Mbytes before 1 Gbayt. DDR SDRAM (Double Date Rate SDRAM) is a synchronous memory, realizing duplicated send rate given in contrast with usual SDRAM.

DDR SDRAM has no full compatibility with SDRAM though uses the method of management, as beside SDRAM, and standard 168-contact connector DIMM. DDR SDRAM reaches duplicated reception capacity to account of the work on both border of the pulsing signal (on ascent and decline), but SDRAM works only on one.

Seoul, Korea, January 20 2003 Company Samsung Electronics, leading supplier leading technology to memories, declares about development first device in industry 4Gbyte DDR DIMM(the module to memories with dual in-line location conclusion). The Module contains in itself thirty six components DDR SDRAM on 1 Gigabit each, which reach density 4Gbyte and can be used for large powered exhibits, for instance, for server, workstation and суперкомпьютеров.

The Leading decisions are from Samsung capable to provide the development and system ensemble creation of the following generation, has said John Kang, senior vice president of the Subdivision of the planning and engineering device to memories in companies Samsung Electronics. Realizing close co-operation with sink-producer, company Samsung offers the new decisions on module DDR high density, which will promote the appearance of the leading computing systems.

The Device 4Gbyte DDR DIMM is created on base of one of the developments Samsung, technologies 0.10 micron. The Operating line of the module 1Gb DDR SDRAM vary from 266Mbps before 333Mbps. Will be released several desksides of the module (-h4, -h8 and -h16 bit) in packing 400mil TSOP2, which is an industry-standards.

The Company Samsung has developed the first industrial module 1Gb DDR SDRAM at December 2002. The Sample were разосланы leading developer of the systems. The Mass production scheduled on the second half 2003. The Company Samsung is an industrial leader in the field of leading decisions of the memories, including speediest device DDR333 and DDR400 and with density 512Mb and 1 Gb. 7.4 миллиарда USA dollar must reach As of exploratory organization Gartner Dataquest market device 1Gb DDR SDRAM to 2006.

XMS-memory

Corsair - a progenitor production to memories XMS (extended Memory Speed), increasing range of the using DDR-modules where needs maximum subsystem capacity to memories. The Individual selection chip and preliminary installing the modules allows to obtain the significant speed increase in desktops hi-end.

Memory for server and workstation

The Modules to memories to high capacity DDR-SDRAM are recommended leading producer hi-end charges, for use in critical to capacity and reliability exhibits. Registrovye or небуферированные, with possibility of support ECC.
In series entered the new models of the type DDR333 (PC2700) and DDR400 (PC3200) by volume from 256 before 512 Mbytes. Besides, engineer Kingston improved technical features already releasing modules HyperX DDR 370 (PC3000) and DDR 434 MHZ (PC3500) CL2: is reduced time of the access of the microcircuits, использующихся in modification by volume 256 and 512 Mbytes.

The Modules Kingston serieses HyperX are intended for admirer of the computer plays and amateurs runaway of system, which is required memory raised to reliability. All modules HyperX are equipped aluminum теплоотводной by plate and are tested on stability of the work on declared frequency. The Height of the printed charge of all modules 30,48 mm. Retail price of the new modules to memories forms from 47 before 207 uSAS dollar.

The Employees iXBT have got in its dictation get fat version to presentations to companies Elpida, submitted for forum Platform Conference 2003. In presentations are presented detailed plans to companies on issue chip and modules to memories DDR I/DDR II, are included concrete features preparing to issue of the modules to memories PC2-4300 (DDR2-533) and PC2-5400 (DDR2-667).

Mainly, stated issue of the modules PC-2700 concern in the document material (DDR-333) on chip in body TSOP, as well as features Registered DIMM modules PC2-4300 (DDR2-533) and PC2-5400 (DDR2-667). However if approach from afar, cost(stand)s to bring total роадмэп companies for nearest years.

We to manage to get rich full 44-paged presentation to companies Elpida, submitted for forum Platform Conference 2003. Prelyubopytneyshiy, shall say you, the document since alongside with detailed plan of the companies on issue chip and modules to memories DDR I/DDR II, comprises of itself concrete features preparing to issue of the modules to memories PC2-4300 (DDR2-533) and PC2-5400 (DDR2-667). Of course, within the framework of news possible to send only the most main thereof document. The Fit.

Mainly, stated issue of the modules PC-2700 concern in the document material (DDR-333) on chip in body TSOP, as well as features Registered DIMM modules PC2-4300 (DDR2-533) and PC2-5400 (DDR2-667). However if approach from afar, cost(stand)s to bring total роадмэп companies for nearest years. What see, memory SDRAM leaves with production of the companies Elpida in the nearest future moreover, both in DIMM, and in SO-DIMM performance. In the near future company intending to concentrate its attention on issue of the modules PC2700 for desk and mobile PC, approximately in втором quarter to begin the production of the modules PC3200. All this pertains to memories DDR I. That concerns the chip of the standard DDR II, to issue which company intending to proceed at the end 2003 begin 2004, that here appears clarity in pinout of the modules of the new standard: for the market desk PC will be released 240-contact Registered modules DIMM DDR II SDRAM, for the market server and workstation - 240-contact Unbuffered modules DIMM DDR II SDRAM, for mobile device - 200-contact modules SO-DIMM and 244-contact modules Mini DIMM DDR-II SDRAM. According to statement stated in the document, company has already conducted test test 240-contact modules DIMM PC2-4300 (DDR2-533) and ready to their production, now all deal "abuts against" in work with standard and the most further сертификацию modules for concrete platforms. Moreover, the first sample chip DDR2 from Elpida, according to the document, correspond to the approximite feature a chip DDR2-667. In brought above table possible to notice that in plan of the companies issue chip DDR2 capacity from 256 Mbit before 4 Gbit, but in prospect terribly say, even 8 Gbit that will result in module by capacity 16 Gb! The Fantasy... Packing the microcircuits DDR2, what communicated earlier - 64-contact chips FBGA ( BGA) and 84-contact FBGA ( BGA), one of the methods of the packing chip in modules company promotes designed by her method TCP (Tape Carrier Package)

Author: А. V. Savin It Is Added: 29.04.2007